The present invention is related generally to emitter coupled logic circuits, and more particularly to high speed emitter coupled logic circuits having diode load circuitry.
In prior art emitter coupled logic circuits, such as that shown and described in U.S. Pat. No. 3,917,959, the load circuitry of the internal switching transistors includes a resistor which is used to provide binary output having a high and low voltage state. However, using a resistor in the load circuit creates a number of problems including temperature stability problems, sensitivity to capacitive loading, limitations in speed of operation and the requirement of a fixed bias current which can only be changed by changing the value of the resistor. The sensitivity to capacitive loading can be decreased somewhat by utilizing a series coupled emitter-follower and diode in addition to a resistor in the load circuit, as illustrated in the aforementioned U.S. Pat. No. 3,917,959. Although such load circuits make it feasible for prior art emitter coupled logic circuits to operate at higher speeds, the maximum speed of operation attainable is limited due to the fact that complete switching is necessary and higher speeds of operation result in relatively high power dissipation. Both high speed operation and at the same time, relatively low power dissipation is required in many applications, such as in high speed dual modulus prescalers utilized in frequency synthesizers used in direct FM radios.